The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to via structures in integrated circuit devices.
As integrated circuit (IC) technologies have advanced, the size of these devices has correspondingly decreased. In particular, as devices are reduced in scale to comply with ever-smaller packaging, tighter constraints are applied to their dimensions and spacings.
As device dimensions are reduced, the line resistance and via resistance within an IC can increase, causing signal propagation delays, and reduced performance of that IC. Copper (Cu) interconnects, in particular, can cause resistance issues as device dimensions shrink, because the thickness of the Cu layer is proportionally larger than its corresponding diffusion barrier layer (e.g., tantalum nitride, TaN). The thinner barrier layer, particularly at the bottom of vias, can fail to effectively prevent electromigration, a significant cause of failure in ICs.